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EM250
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Transmitted character while transmit FIFO was empty (Transmit underrun error)
To generate interrupts to the CPU, the interrupt masks in the INT_SC2CFG and INT_CFG register must be
enabled.
5.3.2
I 2 C Master Mode
The SC2 I 2 C controller is only available in master mode. The SC2 I 2 C controller is enabled with SC2_MODE set to
3. The I 2 C Master controller supports Standard (100kbps) and Fast (400kbps) I 2 C modes. Address arbitration is
not implemented, so multiple master applications are not supported. The I 2 C signals are pure open-collector
signals, and external pull-up resistors are required.
The SC2 I 2 C mode has the following features:
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Programmable clock frequency (400kHz max.)
7- and 10-bit addressing
The following signals can be made available on the GPIO pins:
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SDA (serial data)
SCL (serial clock)
The I 2 C Master controller obtains its reference clock from a programmable clock generator. Clock rates are set
by a clock division ratio from the 24MHz clock:
Nominal Rate = 24MHz / ( 2 * (LIN + 1) * 2 EXP )
EXP is written to the SC2_RATEEXP register and LIN to the SC2_RATELIN register. Table 26 shows the rate
settings for Standard I 2 C (100kbps) and Fast I 2 C (400kbps) operation.
Table 26. I 2 C Nominal Rate Programming
Nominal Rate
100kbps
375kbps
400kbps
SC2_RATELIN
14
15
14
SC2_RATEEXP
3
1
1
Note that, at 400kbps, the I 2 C specification requires the minimum low period of SCL to be 1.3μs. To be strictly
I 2 C compliant, the rate needs to be lowered to 375kbps.
The I 2 C Master controller supports generation of various frame segments defined by the register bits
SC_I2CSTART , SC_I2CSTOP , SC_I2CSEND , and SC_I2CRECV within the SC2_I2CCTRL1 register. Table 27
summarizes these frames.
Full I 2 C frames have to be constructed under software control by generating individual I 2 C segments. All
necessary segment transitions are shown in Figure 7. ACK or NACK generation of an I 2 C receive frame segment
is determined with the register bit SC_I2CACK in the SC2_I2CCTRL2 register.
Generation of a 7-bit address is accomplished with one transmit segment. The upper 7 bits of the transmitted
character contain the 7-bit address. The remaining lower bit contains the command type (“read” or “write”).
Generation of a 10-bit address is accomplished with two transmit segments. The upper 5 bits of the first
transmit character must be set to 0x1E . The next 2 bits are for the 2 most significant bits of the 10-bit
address. The remaining lower bit contains the command type (“read” or “write”). The second transmit
segment is for the remaining 8 bits of the 10-bit address.
120-0082-000V Rev 1.1
Page 66
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